Timing synchronizing circuit for demodulators

ABSTRACT

In a timing synchronizing circuit wherein a timing signal is regenerated from a baseband signal subjected to a bandwidth limitation, there are provided a voltage controlled oscillator whose oscillation frequency varies in accordance with a control signal, an A/D converter which samples and shapes the baseband signal by utilizing the output of the voltage controlled oscillator, a decision circuit for deciding the polarity of a differential coefficient of the baseband signal at an optimum sampling point on the basis of an output of the A/D converter, and a logic circuit responsive to the output of the decision circuit to apply a logical operation to a decision signal derived from the A/D converter and which decides whether or not the baseband signal shifts from a level corresponding to the optimum sampling point, thereby producing the control signal for the voltage controlled oscillator. According to this circuit the regenerated timing signal contains only a negligible amount of jitter components and always maintains an optimum timing without using any phase adjustment.

BACKGROUND OF THE INVENTION

This invention relates to a timing synchronizing circuit forregenerating a timing signal from a baseband signal subjected tobandwidth limitation.

For converting a modulated signal demodulated by a demodulator utilizedin a digitial carrier wave transmission system into a digital signal, atiming signal is necessary. Various means have been proposed forregenerating the timing signal, and a circuit to be described later canregenerate a timing signal containing a small proportion of jittercomponents but this circuit requires phase adjustment.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide a novel timingsynchronizing circuit capable of obtaining a regenerated timing signalcontaining less jitter components and always maintaining an optimumtiming without using phase adjustment.

According to this invention, there is provided a timing synchronizingcircuit wherein a timing signal is regenerated from a baseband signalsubjected to a bandwidth limitation, characterized in that there areprovided a voltage controlled oscillator whose oscillation frequencyvaries in accordance with a control signal, an A/D converter whichsamples and shapes the baseband signal by utilizing the output of thevoltage controlled oscillator, a decision circuit for deciding thepolarity of a differential coefficient of the baseband signal at anoptimum sampling point on the basis of an output of the A/D converter,and a logic circuit responsive to the output of the decision circuit toapply a logical operation to a decision signal derived from the A/Dconverter and which decides whether or not the baseband signal shiftsfrom a level corresponding to the optimum sampling point, therebyproducing the control signal for the voltage controlled oscillator.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram showing a prior art timing synchronizingcircuit;

FIG. 2 is a block diagram showing one embodiment of the timingsynchronizing circuit according to this invention;

FIG. 3a shows waveforms useful to explain the operation of the circuitshown in FIG. 2;

FIG. 3b shows sampling points for the waveforms shown in FIG. 3a;

FIG. 4 is a block diagram showing examples of a decision circuit and alogic circuit shown in FIG. 2;

FIG. 5 is a connection diagram of an amplitude comparator shown in FIG.4;

FIG. 6 is a block diagram showing a modification of the timingsynchronizing circuit according to this invention;

FIG. 7 is a diagram for explaining the operation of the modificationshown in FIG. 6;

FIG. 8 is a block diagram showing a decision circuit shown in FIG. 6;

FIG. 9 is a block diagram showing a prior art demodulator apparatusincluding a timing synchronizing circuit and a demodulation circuit incombination, which is adapted for demodulation of 4 PSK (4-phase phaseshift keying) waves;

FIG. 10 is a block diagram showing a first embodiment of demodulatorapparatus according to the present invention which is adapted fordemodulation of 4 PSK waves;

FIG. 11 is a block diagram showing a second embodiment of demcodulatorapparatus according to the present invention adapted for demodulation of16 QAM (16-level quadrature amplitude modulation) waves;

FIG. 12 is a block diagram showing a third embodiment of demodulatorapparatus of the invention adapted for demodulation of 4 PSK waves;

FIG. 13 is a block diagram showing a fourth embodiment of demodulatorapparatus of the invention adapted for demodulation of 16 QAM waves; and

FIG. 14 is a block diagram showing a fifth embodiment of demodulatorapparatus of the invention adapted for demodulation of 64 QAM waves.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Firstly, a prior art timing signal regenerating circuit will bedescribed with reference to FIG. 1. This circuit comprises a full-waverectifier 2; a phase synchronizing circuit 3 including a phasecomparator 4, a voltage controlled oscillator 5 and a low-pass filter 6;a phase shifter 7; and a one bit A/D converter 8. FIG. 1 shows a casewherein the modulation wave is a two-phase PSK wave. This circuitoperates as follows. An inputted PSK signal is demodulated at a phasedetector 1 by using a reference carrier wave to produce a two-valuebaseband signal. The demodulated baseband signal is supplied to thefull-wave rectifier 2 where the frequency of the demodulated basebandsignal is doubled to extract a timing signal. The extracted signal isthen supplied to the ordinary phase synchronizing circuit 3 to obtain aregenerated timing signal containing less jitter components, theregenerated timing signal being phase synchronized with the extractedtiming signal and limited in a narrow bandwidth. The output of the phasesynchronizing circuit 3 is supplied to the A/D converter 8 via the phaseshifter 7 and used as the timing signal for sampling and shaping thedemodulated baseband signal. At this time, it is necessary to adjust thephase of the regenerated timing signal with the phase shifter 7 so thatthe demodulated baseband signal would be sampled at an optimum timing.With this circuit, although it is possible to regenerate a timing signalcontaining less jitter components, it is necessary to adjust the phase.

The invention contemplates provision of an improved timing synchronizingcircuit not requiring phase adjustment.

A preferred embodiment of a timing signal synchronizing circuit of thisinvention shown in FIG. 2 comprises a voltage cotrolled oscillator 5, alow-pass filter 6, a logic circuit 9, a decision circuit 10, and atwo-bit A/D converter 11. FIG. 3a shows waveforms for explaining theoperation of the embodiment shown in FIG. 2.

The operation of this embodiment will now be described. It is nowassumed that the demodulated baseband signal m of the output of thephase detector 1 has been somewhat subjected to bandwidth limitation,and that the baseband signal contains signals m₁ to m₄ having waveformresponse as shown in FIG. 3a. Such a demodulated baseband signal issampled by the A/D converter 11 and converted into data signals X₁ andX₂ according to reference levels L₁, L₂ and L₃. The reference level L₂is typically zero volt and binary value of the data signal X₁ isdetermined with respect to this level L₂. At the levels L₁ and L₃, themaximum margin for the signals m₁ to m₄ is obtained. The relation amongthe demodulated baseband signal m and data signals X₁ and X₂ is as shownin the following Table I. The data signal X₂ which takes a binary valueaccording to Table I serves to decide whether or not the baseband signalm, particularly, signals m₁ to m₄ shift from levels corresponding tooptimum sampling points A₋₁, a₋₁, B₀, b₀, C₁ and C₁ meeting the maximummargin.

                  TABLE I                                                         ______________________________________                                        Demodulated baseband signal m                                                                        X.sub.1                                                                             X.sub.2                                          ______________________________________                                        m > L.sub.1            1     1                                                L.sub.2 < m < L.sub.1  1     0                                                L.sub.3 < m < L.sub.2  0     1                                                m < L.sub.3            0     0                                                ______________________________________                                    

In FIG. 3_(b), T₋₁, T₀ and T₁ represent optimum sampling pointsthroughout 3 time slots. When the signals m₁ to m₄ having waveformresponse are sampled at the optimum sampling points T₋₁, T_(o) and T₁meeting the maximum margin, the binary value "1" or "0" of the datasignal X₂ that decides whether or not the demodulated baseband signal mshifts from levels corresponding to the optimum sampling points would beoutputted at an equal probability. However, when the baseband signal issampled at a timing T_(o) +Δt or T₀ -Δt, the data signal X₂ assumesbinary values as shown in the following Table II in accordance withwaveforms of the baseband signal.

                  TABLE II                                                        ______________________________________                                        sam-         waveform                                                         pling        Data Signal X.sub.2                                              point        m.sub.1                                                                             m.sub.2     m.sub.3                                                                           m.sub.4                                    ______________________________________                                        T.sub.0 + Δt                                                                         1     1           0   0                                          T.sub.0 - Δt                                                                         0     0           1   1                                          ______________________________________                                    

Table II shows that for the signals m₁ and m₂ having a positivedifferential coefficient at point T₀, the data signal X₂ is always "1"when the sampling point shifts from the optimum sampling point by +Δtwhereas the data signal X₂ is always "0" when the sampling point shiftsby -Δt. On the other hand, for the signals m₃ and m₄ having a negativedifferential coefficient at point T₀, the polarity of the data signal X₂is inverted in comparison with the polarity of the data signal X₂obtained with the signal m₁ and m₂. Therefore, the data signal X₂ forthe signals m₃ and m₄ is made identical to that for the signals m₁ andm₂ by inverting the polarity of the data signal X₂. As described above,when the polarity of the differential coefficient of the demodulatedbaseband signal at an optimum sampling point T₀ is decided, and when alogical operation is executed according to results of the decision, asignal representative of a result of the logical operation can be usedas an error signal which detects shifting of the sampling point. Thedecision circuit 10 shown in FIG. 2 decides gradients of signals m₁ tom₄, and provides output signals G and G deciding the gradients of thesignals m₁ to m₄. The output signal G becomes "1" for the signals m₁ andm₂ whereas the output signal G becomes "1" for m₃ and m₄. The logiccircuit 9 includes a circuit which inverts the polarity of the signal X₂when the signal G is "1" and holds a data signal X₂ which corresponds toone of the signals m₁ to m₄ and occurs in the nearest precedence whenboth the signals G and G are zero. The output of the logic circuit 9produces an error signal APC that detects the shifting of the samplingpoint in the A/D converter 11. Accordingly, when the output of the logiccircuit 9 is supplied through the low-pass filter 6 to the voltagecontrolled oscillator 5 as a control signal, the circuit shown in FIG. 2always supplies a timing signal to the A/D converter 11 at an optimumtiming.

FIG. 4 is a block diagram showing preferred examples of the logiccircuit 9 and the decision circuit 10 in which reference numerals 12 to16 and 24 designate D type flip-flop circuits, 17 an amplitudecomparator, 18 an OR/NOR gate circuit, 19 and 20 OR gate circuits and 21to 23 AND gate circuits. The flip-flop circuits 12 and 14 act as a 3-bitmemory circuit, and the outputs Y₁ and Y₋₁ of the flip-flop circuits 12and 14 are inputted to the amplitude comparator 17. The amplitudecomparator 17 decides the polarity of the differential coefficient ofthe demodulated baseband signal at the optimum sampling point T₀ in theA/D converter by comparing data at points T₋₁ and T₁. Thus, when thedata signal X₁ changes from "0" to "1" at the reference level L₂, thepolarity of the differential coefficient is positive whereas when thedata signal X₁ changes from "1" to "0", the differential coefficient isnegative. The output signals G and G deciding the gradients of thesignals m₁ to m₄ are outputted from the amplitude comparator 17, whereinG becomes "1" for signals m₁ and m₄ while G becomes "1" for signals m₃and m₄. When, that is, the gradient of the signal having the waveformresponse is positive, the gate circuits 20 to 22 pass the data signal X₂without changing its polarity whereas when signal G is "1", that is, thegradient of the signal having the waveform response is negative, passthe data signal X₂ after inverting the polarity thereof. When either oneof the signals G and G is "1", AND gate circuit 23 sends out a timingsignal whereas when signals G and G are both "0", indicating that thewaveform response signal is flat the output of the AND gate circuit 23is "0". Consequently, for the waveform response signals m₁ to m₄, theflip-flop circuit 24 outputs the output of OR gate circuit 20 as it isand in the case other than m₁ to m₄, the flip-flop circuit 24 holds adata signal X₂ which corresponds to one of the signals m₁ to m₄ andoccurs in the nearest precedence.

FIG. 5 shows an example of the amplitude comparator 17 which comprisesOR/NOR gate circuits 25 and 26, and AND gate circuits 27 and 28.

FIG. 6 shows an embodiment in which the demodulated baseband signalobtained by detecting a QAM wave has four values. In this embodiment,3-bit A/D converter 29, and a corresponding decision circuit 30 areused.

FIG. 7 is a table for explaining the operation of the circuit shown inFIG. 6 and shows the four-value baseband signal in relation to outputsX₁ to X₃ of the converter 29. Four values are present at referencelevels L₁₁, L₃₁ (L₁₂), L₃₂ (L₁₃) and L₃₃ representative of the maximummargin for four values. Levels L₂₁ and L₂₃ are reference levels withrespect to which binary values "1" and "0" of data signal X₂ aredetermined. Similarly, level L₂₂ is a reference level with respect towhich binary values "1" and "0" of data signal X₁ are determined. Datasignal X₃ serves to decide whether or not waveform response signalsshift from levels corresponding to optimum sampling points. Thus, forthe demodulated baseband signal having four values, the data signal X₃is inputted to the logic circuit 9. The decision circuit 30 outputssignals G and G having the same performance as those shown in FIG. 2 andthese output signals are inputted to the logic circuit 9. Consequently,the logic circuit 9 outputs an error signal APC that detects shifting ofthe sampling point. When this error signal is applied to the voltagecontrolled oscillator 5 as a control signal, the circuit shown in FIG. 6can be applied to the four-value demodulated baseband signal. Then, thecircuit operates as a timing synchronizing circuit.

FIG. 8 shows an example of the decision circuit 30 comprising D typeflip-flop circuits 31 to 36 and an amplitude comparator 37. The decisioncircuit operates as follows. As the outputs of flip-flop circuits 31 and34 can be obtained data Y₁ of the signals X₁ and X₂ at time T₁ whiledata Y₋₁ of signals X₁ and X₂ at time T₋₁ can be obtained as the outputsof flip-flop circuits 33 and 36 so that these outputs are applied to theamplitude comparator 37 so as to decide the polarity of the differentialcoefficient of the demodulated baseband signal. Let us denote thefour-value signal at time T₋₁ by AT₋₁, the four-value signal at time T₁by AT₁, AT₁ -AT₋₁ =M is calculated by the amplitude comparator 37. WhenM is positive, that is, when the differential coefficient at time T₀ ispositive, output G is "1", whereas when M is negative, that is, when thedifferential coeffcient at a time T₀ is negative, output G is "1". Thefour-value signals AT₋₁ and AT₁ can be obtained by the logical operationof the outputs of flip-flop circuits 31, 33, 34 and 36.

Although, in the foregoing description, embodiments of this inventionapplicable to two-value and four-value demodulated baseband signal havebeen described, it should be understood that the invention is alsoapplicable to much more valued baseband signals. For example, in thecase of a 4-phase PSK wave, the PSK wave is branched into two having 90degree phase difference and then the branched waves are supplied to thecircuit shown in FIG. 2. In the case of a 16-value QAM wave, the QAM isbranched into two having 90 degree phase difference and these twobranched waves are supplied to the circuit shown in FIG. 6 respectivelyvia detectors.

As described above, this invention is applicable to a baseband signalsubjected to a bandwidth limitation. In the embodiments, it is assumedthat waveform response signals as shown in FIG. 3a occur as a result ofthe bandwidth limitation but it will be clear that as the condition forlimiting the bandwidth varies, the waveform response signals shown inFIG. 3a vary. In such a case, it is necessary to modify the decisioncircuit 10 or 30 so as to satisfy the condition. In the embodimentsshown in FIGS. 2 and 6, a timing synchronizing circuit utilized in adigital carrier wave transmission system was described, but it should beunderstood that the invention is not limited to such an application, andthe invention is also applicable to a baseband transmission system inwhich a baseband signal as shown in FIG. 3a is transmitted. Examples ofthe decision circuits were shown in FIGS. 4 and 8, the decision circuitbeing required to have a performance that decides the polarity of thedifferential coefficient of the baseband signal at the sampling time.Accordingly, various means other than those shown in FIGS. 4 and 8 canbe used.

Practically, the timing synchronizing circuit of the present inventiondescribed previously has widespread applications in obtaining datasignals from 4-PSK wave, 16 QAM wave, or 64 QAM wave.

Thus, a prior art demodulation apparatus for 4 PSK wave as shown in FIG.9 has been available which includes a timing synchronizing circuit 900being the same as that of FIG. 1 with the only exception that an A/Dconverter 91 is a two-bit A/D converter and an additional channelcomprised of a phase detector 93 and an A/D converter 92 is provided forgeneration of data 2, and a demodulation circuit 901. The demodulationcircuit 901 comprises a carrier synchronizing circuit 94 responsive tothe output data signals of the timing synchronizing circuit 900 toproduce a reference carrier frequency, and a phase detector 1 andanother phase detector 93 which respectively respond to the referencecarrier frequency directly and via a 90 degree phase shifter 95 so as todemodulate a 4 PSK wave applied to the phase detectors 1 and 93.

The carrier synchronizing circuit 94 comprises a section including anexclusive OR gate 94-1 with its inputs connected via terminals C₃ and C₄to a data signal Y₁ from the A/D converter 92 and a data signal X₂ fromthe A/D converter 91, an exclusive OR gate 94-2 with its inputsconnected via terminals C₂ and C₁ to a data signal X₁ from the A/Dconverter 91 and a data signal Y₂ from the A/D converter 92, and asubtractor 94-3 applied with outputs of the exclusive OR gates 94-1 and94-2. This section is responsive to the outputs of the A/D converters 91and 92 to generate an error signal for detecting the rotationaldirection of the respective waveform response signals of the 4 PSK wave.In addition to this error signal generating section, the carriersynchronizing circuit 94 has a low-pass filter 94-4 responsive to theoutput of the subtractor 94-3, and a voltage controlled oscillator 94-5controlled by the output of the low-pass filter to produce the referencecarrier frequency supplied to the phase detector 1 and 90 degree shifter95 via a terminal C.sub. 5.

The carrier synchronizing circuit 94 operates as follows. Data signalsY₂ and X₁ are exclusive ORed at the exclusive OR gate 94-2 so that thisgate 94-2 produces an output "0" when the respective waveform responsesignals of the 4 PSK wave rotate counterclockwise. Data signals X₂ andY₁ are exclusive ORed at the exclusive OR gate 94-1 which , in turn,produces an output "1" when the respective waveform response signalsrotate counterclockwise. Thus, by subtracting the output signals of thetwo exclusive OR gates 94-1 and 94-2 at the subtractor 94-3, a "0"signal of doubled level can be obtained. This doubled "0" level outputis passed through the low-pass filter 94-4 for suppression of noises andsupplied to the voltage controlled oscillator 94-5 which then produces acarrier signal in synchronism with the input 4 PSK wave.

With the FIG. 9 demodulation apparatus, the input 4 PSK wave can bedemodulated at the demodulation circuit 901 and converted into data 1and 2 at optimum sampling points at the timing synchronizing circuit900. Disadvantageously, this demodulation apparatus requires phaseadjustment as described with reference to FIG. 1.

FIGS. 10 to 14 show various embodiments of demodulation apparatusaccording to the present invention which can obviate the prior artdrawback. Throughout FIGS. 10 to 14, demodulation circuits 109, 113,123, 133 and 143 each including a carrier synchronizing circuit 94,phase detectors 103 and 104, and a 90 degree phase shifter 107 have thesame construction as that of the demodulation circuit 901 shown in FIG.9 but the connection of the demodulation circuit to timing synchronizingcircuit 108, 112, 122, 132 or 142 is different from the connection ofthe demodulation circuit 901 to the timing synchronizing circuit 900shown in FIG. 9.

FIG. 10 shows an embodiment of demodulation apparatus of the inventionadapted for demodulation of 4 PSK waves. The timing synchronizingcircuit 108 is constituted by clock synchronizing circuits 101 and 102,and A/D converters respectively associated with the circuits 101 and102. Each of the clock synchronizing circuits 101 and 102 includes avoltage controlled oscillator 5, a low-pass filter 6, a logic circuit 9and a decision circuit 10 connected to each of the A/D converters 105and 106 in the same manner as in FIG. 2. Data signals X₁ standing fordata 1 and X₂ from the A/D converter 105 are also applied to the carriersynchronizing circuit 94 via terminals C₂ and C₃, and data signals Y₁standing for data 2 and Y₂ from the A/D converter 106 are also appliedto the carrier synchronizing circuit 94 via terminals C₄ and C₁.

FIG. 11 shows an embodiment of demodulation apparatus of the inventionadapted for demodulation of 16 QAM waves. In this embodiment, a timingsynchronizing circuit 112 includes a clock synchronizing circuit 111including a voltage controlled oscillator 5, a low-pass filter 6, alogic circuit 9 and a decision circuit 30 connected to each of the A/Dconverters 105' and 106' in the same manner as in FIG. 6. Data signalsX₁ standing for data 1-1 and X3 from the A/D converter 105' are alsoapplied to the carrier synchronizing circuit 94 via terminals C₂ and C₃,data signals Y₁ standing for data 2-1 and Y₃ from the A/D converter 106'are also applied via terminals C₄ and C₁.

The FIG. 10 embodiment is modified as shown in FIG. 12 which isdifferent therefrom in that the timing signal is supplied in common tothe two A/D converters 105 and 106, thereby ensuring that only one clocksynchronizing circuit 101 (102) can suffice.

The FIG. 11 embodiment is modified as shown in FIG. 13. Thismodification is different from the FIG. 11 embodiment in that the clocksynchronizing circuit 111 is replaced with the circuit 101 (102) tosimplify the circuit construction.

FIG. 14 shows an embodiment of demodulation apparatus according to thepresent invention which is adapted for demodulation of 64 QAM waves.This embodiment is the same as the FIG. 13 embodiment with the onlyexception that the bit number of the A/D converters 105" and 106" isincreased.

What is claimed is:
 1. A timing synchronizing circuit for regenerating atiming signal from a baseband signal subjected to a bandwidthlimitation, comprising:voltage controlled oscillator means responsive toa control signal for providing said timing signal; A/D converter meansresponsive to said timing signal for sampling said baseband signal andconverting it into a plurality of digital signals; decision circuitmeans responsive to an output of said A/D converter means for decidingthe polarity of a differential coefficient of said baseband signal at anoptimum sampling point; and logic circuit means responsive to the outputof said decision circuit means for deciding whether or not said basebandsignal shifts from a level corresponding to said optimum sampling point,thereby providing said control signal.
 2. A timing synchronizing circuitaccording to claim 1 wherein said control signal is applied to saidvoltage controlled oscillator via a low-pass filter.
 3. A demodulationapparatus comprising in combination a demodulation circuit fordemodulating a carrier wave modulated with a baseband signal subjectedto a bandwidth limitation and a timing synchronizing circuit forregenerating a timing signal from the demodulated baseband signal;saidtiming synchronizing circuit including a plurality of A/D convertermeans responsive to said timing signal for sampling said demodulatedbaseband signal and providing a plurality of digital signals; and atleast one clock synchronizing circuit including a voltage controlledoscillator responsive to a control signal for providing said timingsignal, a decision circuit reponsive to said timing signal and an outputof said A/D converter means for deciding the polarity of a differentialcoefficient of said baseband signal at an optimum sampling point, and alogic circuit responsive to said timing signal, the output of saiddecision circuit and the output of said A/D converter means, fordeciding whether or not said baseband signal shifts from a levelcorresponding to said optimum sampling point, thereby providing saidcontrol signal; said demodulation circuit including a carriersynchronizing circuit responsive to the outputs of said timingsynchronizing circuit for providing a reference carrier wave, a pair ofphase detectors for detecting the modulated carrier wave with saidreference carrier wave and providing said demodulated baseband signal.4. A demodulation apparatus according to claim 3 comprising a pluralityof clock synchronizing circuits respectively associated with theplurality of A/D converters.
 5. A demodulation apparatus according toclaim 3 wherein said A/D converters are responsive to the timing signalproduced from a single clock synchronizing circuit.